DVCon 2012: 131-II287: Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF

Power management is a critical feature of today’s SoCs, almost as important as functionality. IEEE 1801TM-2009 UPF enables specification of the intended power management infrastructure for an SoC to enable early verification and to drive implementation. Just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, the complexity of the power management infrastructure for an SoC similarly requires a hierarchical methodology that enables separation of concerns and supports partitioning, parallel development, and reuse. In this paper, we propose a hierarchical methodology for the use of IEEE Std 1801TM-2009 UPF (aka UPF 2.0) for the specification of power intent for low power SoCs. This methodology enables verification at the IP block level, hierarchical composition of complex system-level power intent specifications from IP block power intent specifications, and automatic consistency checking to ensure that IP block constraints are met by the system in which they are used. The proposed methodology is illustrated in the context of a complex SoC design architecture that was used to validate the concepts. Index Terms — Functional Verification, Hierarchical composition, IP Reuse, Low Power, Methodology, SoC Integration, UPF.